This invention relates to a MOS (metal oxide semiconductor) dynamic memory cell having one MOS transistor and one MOS capacitor and a method of fabricating the same.
In order to fabricate a MOS dynamic memory device by integrating minature memory cells at a high density it is essential to reduce the thickness of the oxide film of each memory cell, the depth of a diffused layer, the voltage of a power supply applied to the memory cell, ect., according to a predetermined definite ratio that is by using so-called proportional reducing technique. For example, for fabricating an integrated circuit for use in a MOS dynamic memory device having a capacity of 16K bits the power supply voltage may be 12 V, and the bias voltage applied to a semiconductor substrate may be -5 V, whereas in the case of a MOS dynamic memory device having a capacity of 64K bits, it is generally necessary to use a single power supply of 5 V and to use a pattern size of 3 to 4.mu. rule for the MOS memory cell.
Where a memory cell is constituted by one MOS transistor and one MOS capacitor, the MOS transistor and the MOS capacitor are juxtaposed so that writing information into the MOS capacitor in the form of potential and reading out the stored information can be accomplished by controlling the turning ON and OFF of the MOS transistor. In a memory cell constructed as above described, however, as the inversion voltages of the MOS transistor and MOS capacitor increase owing to so-called back bias effect (that is an effect in which the threshold voltage of the MOS transistor varies according to the voltage between the source and substrate of the MOS transistor) the potential stored into the cell, that is the potential stored into the MOS capacitor decreases to about 75% of the voltage of a power supply. Thus for example, for a voltage of the power supply of 12 V, the voltage written into the MOS capacitor decreases to about 9 V and for a voltage of the power supply of 5 V, the voltage written into the MOS capacitor decreases to about 3.75 V. The difference between the voltage of a power supply and voltage being written into the MOS capacitor is deemed as a loss.
Let us consider the inversion voltage or threshold voltage of the MOS transistor and the MOS capacitor.
Upon application of a gate voltage upon the gate electrode of the MOS transistor, an electric field is formed in a region of the semiconductor substrate of a first conductivity type confronting the gate electrode so that the minority carriers presenting in the substrate are collected in the surface of the region whereby the surface of that region would become a second conductivity type to form a channel. The MOS transistor is rendered ON when the channel is formed, whereas is rendered OFF when the channel is not formed. The minimum gate voltage at which a channel is formed is termed the inversion voltage or threshold voltage, the former V.sub.T is expressed by the following equation (1) ##EQU1## when V.sub.FB represents the flat band voltage (which will be described later in detail), Q.sub.FP the Fermi level of the substrate, C.sub.O the capacity per unit area of the MOS transistor and Q.sub.B is expressed by the following equation (2) ##EQU2## where .epsilon..sub.s : the specific dielectric constant of the substrate
.epsilon..sub.o : dielectric constant under vacuum PA1 g: unit charge PA1 N.sub.A : impurity concentration of the substrate PA1 V.sub.RS : the source potential of the MOS transitor to the substrate.
Equation (1) is also applicable to a MOS capacitor, in which case V.sub.T represents the threshold voltage of the MOS capacitor, C.sub.O the capacitance of the MOS capacitor, V.sub.RS the voltage around the MOS capacitor to the substrate.
As can be noted from equation (1) when the gate voltage of the MOS transistor is lower than the invention or threshold voltage expressed by equation (1) the MOS transistor does not turn ON, and since the inversion voltage increases with the source voltage it is necessary to increase the gate voltage in order to maintain the MOS transistor in the conductive state. Where the gate voltage of the MOS transistor is maintained at a constant value larger than the threshold voltage an information is written into the MOS capacitor in the form of voltage via a digital line connected to the source electrode of the MOS transistor. As a consequence, the voltage of the MOS capacitor increases gradually so that the inversion voltage of the MOS transistor also increases with the voltage of the MOS capacitor. Denoting the constant gate voltage by V.sub.G, and the voltage written into the MOS capacitor by V.sub.C, the value (V.sub.G -V.sub.C) decreases with increase in the voltage of the MOS capacitor.
At a time when a conditions EQU V.sub.G -V.sub.C &lt;V.sub.T
is satisfied, as the MOS transistor turns OFF, a voltage higher than V.sub.C can not be written into the MOS capacitor as long as the gate voltage V.sub.G is constant. Increase in the inversion voltage of the MOS capacitor results in the some tendency as the increase in the inversion voltage of the MOS transistor.
A disadvantage caused by the increase in the threshold voltage of the MOS capacitor can be prevented by rendering the surface of the semiconductor substrate facing an electrode of the MOS capacitor to have a conductivity type opposite to that of the substrate as disclosed in Japanese Patent Publication No. 13252/1973. This method, however, requires provision of a diffused layer which interconnects the MOS transistor region and the MOS capacitor region. Such diffused layer prevents increase in the density of integration of the memory cells. A memory cell not requiring such diffused layer is disclosed in Japanese laid open patent specification No. 137399/1976. In this memory cell, an extension of the gate electrode of the MOS transistor region disposed adjacent to one end of the MOS capacitor region is arranged on an electrode of the MOS capacitor region through an insulating layer, such structure being termed a double polycrystalline silicon structure, and can eliminate a diffused region interconnecting the MOS transistor region and the MOS capacitor region.
In the memory cell constructed as above described, although it is desirable to construct the MOS transistor to operate in an enhancement mode and the MOS capacitor in a depletion mode, it is extremely difficult to obtain such construction. More particularly, according to a prior art method of fabricating a MOS capacitor of a depletion mode, ions of phosphor or arsenic were implanted into the surface of a substrate corresponding to the MOS capacitor region. Such ion implantation step requires use of an IC mask. Use of the IC mask inherently results in an alignment error so that it is necessary to completely shield a region other than the region to be implanted with ions with a mask. It can be understood that it is extremely difficult to form a MOS transistor region adjacent to the region implanted with ions, that is at a portion closely adjacent to the MOS capacitor region, when one considers the alignment error described above. For the purpose of preventing ion implantation into a portion of the MOS transistor region close to the MOS capacitor region, if the mask were shifted towards the MOS capacitor region, the ion implantation would not be made in a region interconnecting the MOS transistor and the MOS capacitor. For this reason, a potential barrier would be formed in the interconnecting region, thus failing to manifest an effect obtainable by forming the MOS capacitor to operate in a depletion mode. This is the reason why it has been difficult to form the MOS capacitor to have a depletion mode in the prior art memory cell in which the MOS capacitor and the MOS transistor were disposed closely. For this reason, due to the above described back bias effect, a voltage of only about 75% of the power supply voltage could be written into the MOS capacitor.
In such a case, the following disadvantage occurs. The level of a single V.sub.S read out from the memory cell can approximately be given by the following equation EQU V.sub.S =(C.sub.C /C.sub.P)V.sub.C
where C.sub.C represents the capacitance of the MOS capacitor, C.sub.P a stray capacitance presenting on one digit line of a dynamic RAM constituted by the memory cells described above, and V.sub.C a potential written into the MOS capacitor. When V.sub.C is small, V.sub.S is also small. As the V.sub.S becomes small the signal read out will be affected by noises. Further, the sensing range of a sense amplifier utilized to read out the signal from the memory cell would be narrowed. Moreover as the amount of charge stored in the memory cell is small it is necessary to make short the refresh interval. In order not to make small the amount of charge it is necessary to increase the size of the chip, thus increasing the cost of manufacturing.
Various problems to be solved in a memory cell wherein a MOS transistor region and a MOS capacitor region are disposed closely adjacent have been discussed above. These problems involves the necessity of increasing the voltage to be written into the MOS capacitor up to substantially the power supply voltage, not to diminish the inversion layer of the MOS capacitor region even when a voltage information is written into the MOS capacitor, and the necessity of eliminating a diffused layer interconnecting the MOS transistor region and the MOS capacitor region, thus reducing the size of the chip.